1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to a structure of a static semiconductor memory device that allows stable writing and reading of data even under operation conditions of a low voltage.
2. Description of the Background Art
When transistor elements are miniaturized according to the progression of miniaturization technologies, voltage scaling depending on the miniaturization is required in view of reliability of the elements and power consumption. As the miniaturization is performed, an influence of variations in manufacturing parameter increases, and causes large variations in threshold voltage of transistors (i.e., insulated gate field-effect transistors to be referred to as “MOS transistors” hereinafter) that form a memory cell. Consequently, it becomes difficult in a semiconductor memory device to perform stable writing and reading of data with a low power supply voltage.
Various structures have been proposed for stably writing and reading data even with such a low power supply voltage.
An article 1 (K. Zhang et al., “A 3-GHz 70 Mb SRAM in 65 nm CMOS Technology with Integrated Column-Based Dynamic Power Supply”, ISSCC 2005, Digest of Technical Papers, February 2005, pp. 474-475) has disclosed a structure which switches a level of a memory cell power supply voltage between those for data reading and data reading, and thereby improves a static noise margin SNM and a write margin.
In this article 1, a memory cell power supply voltage is controlled a memory cell column at a time. In a data write operation, the memory cell power supply voltage in a selected column is set to a low voltage VCC-LO, and the cell power supply voltage in unselected columns is set to a slightly high voltage VCC-HI that is substantially equal to that in a read operation. In the read operation, the cell power supply voltage is kept at high voltage VCC-HI so that a static noise margin in the data read operation is improved. Also, in the write operation, the memory cell power supply voltage is set to low voltage VCC-LO so that a write margin is ensured.
An article 2 (M. Yamaoka et al., “Low-Power Embedded SRAM Modules with Expanded Margins for Writing”, ISSCC 2005, Digest of Technical Papers, February 2005, pp. 480-481) has disclosed a structure that sets a memory cell power supply line in a selected column to a floating state in a data write operation, and sets memory cell power supply lines in the other, i.e., unselected columns to a predetermined voltage level similar to that in a read operation. This article 2 has also disclosed a structure that uses a dummy bit line to produce a word line deactivation timing signal WOFF according to a potential of this dummy bit line, and thereby deactivates a word line driver to drive a selected word line to an unselected state.
In the structure disclosed in this article 2, each word line is provided with a discharge transistor (i.e., a transistor for discharging) that sets the word line to a ground voltage level and is independent of a word line driver. This discharge transistor stays off during a standby state. When a selected word line is to be driven to an inactive state, the discharge transistor rapidly drives the word line to the unselected state by its large current drive power. After it drives the word line to the unselected state, a power supply to this word line driver is interrupted so that a gate potential of the discharge transistor attains the L-level according to the driver power supply voltage to turn off the discharge transistor.
A publication 1 (Japanese Patent Laying-Open No. 2005-038557) has disclosed a structure in which a level changing circuit is used in a word line driver, and a selected word line is driven with a voltage amplitude different from that of a memory cell power supply voltage. By changing the potential of the selected word line, it is intended to improve write and read margins even when variations occur in threshold voltage of a memory cell transistor.
In the structure disclosed in the article 1, switching of the level of the memory cell power supply voltage is controlled a memory cell column at a time. Therefore, two kinds of voltages are required as the memory cell power supply voltage, which results in a problem that a structure achieving the two kinds of power supplies becomes complicated.
Although the memory cell power supply voltage is switchable between different levels, these voltage levels are fixed potentials produced by an internal power supply circuit. Therefore, even when a threshold voltage of the memory cell transistor varies due to variations in process parameter, the voltage level does not change according to such variations, and it is difficult to compensate for the changes in threshold voltage. Therefore, it is difficult to ensure reliably the write and read margins when changes or the like occur in electric characteristics such as a threshold voltage of the memory cell transistor.
In the structure disclosed in the article 2, the memory cell power supply line in the selected column attains the floating state in the data write operation, and lowers the power supply voltage of the memory cells in the write column so that the write margin may be ensured. Although this article 2 has disclosed the improvement of the write margin and the reduction of the power supply current, any consideration is given to a method of improving the read margin when variations occur in threshold voltage of the memory cell transistor.
In the structure disclosed in the reference 1, the memory cell transistor is formed of a Thin Film Transistor (TFT). Even when the threshold voltage thereof varies, the level changing circuit changes a potential amplitude of the selected word line for improving the write and read margins. More specifically, in the data write operation, the structure in this reference 1 drives the selected word line to a potential level higher than the memory cell power supply potential, and thereby increases a current drive power of an access transistor in the memory cell so that fast writing may be performed and the write margin may be ensured. In the data read operation, the structure drives the selected word line to a voltage level lower than a high-side power supply voltage of the memory cell. Since the gate potential of the access transistor in the memory cell lowers, the current drive power lowers, and thereby the static noise margin is ensured so that data destruction may be prevented in the data read operation.
In the structure disclosed in this publication 1, however, the level changing circuit is supplied with an operation power supply voltage from a system different from that for the memory cell power supply voltage, and the shifted voltage level thereof is fixed and is not affected by the threshold voltage of the memory cell. In the reference 1, it is necessary to employ a system of the power supply for the level shifting independent of that of the memory cell power supply so that the power supply systems have a complicated structure. Although the level of the potential of the selected word line is shifted, the voltage level thereof is fixed, and it cannot flexibly follow the variations in threshold voltage of the memory cell transistor.
In the reference 1, the selected word line is driven to the voltage level higher than that of the memory cell power supply in the data write operation, and no consideration is given to the stability of the data in unselected memory cells connected to the selected row in the data write operation.
In the semiconductor memory device, when an operation environment (operation temperature) changes, characteristics of the memory cell transistor changes with it. Therefore, from the viewpoint of reliably ensuring the write and read margins, it is desired to set the voltage level of the selected word line to the optimum value depending on operation environments such as an operation temperature. In the foregoing reference 1 and articles 1 and 2, however, such a structure is neither disclosed nor suggested that reliably adjusts the selected word line according to variations in threshold voltage of the transistor in the memory cell when the foregoing operation environment changes.